Digital to analog converters or DACs are well known in the art for providing an interface between the digital and the analog realm. The DAC functions by converting a digital, usually binary, input code to a corresponding analog signal, typically voltage or current. They may be implemented in a variety of fashions such as for example using simple switches or a network of resistors, capacitors or current sources. Examples of known DAC arrangements include the following U.S. Pat. Nos. 7,015,847, 5,969,657 and 4,491,825 all of which are co-assigned to the assignee of the present invention.
In a segmented DAC architecture it is sometimes useful to provide a buffer between the output of a first DAC and the input of a second DAC. Such buffers may be provided by amplifiers with high common mode linearity which provide the necessary buffering function yet do not contribute significant integral non linearity (INL) errors at the output of the DAC. While this may provide the necessary buffering function, the use of such amplifiers does suffer in that they often require large compensation capacitors to make the amplifier stable with the result that the implementation is very area intensive.
There is therefore a need to provide a buffer arrangement for the input of a DAC that does not contribute significant INL error to the output of the DAC and yet can be implemented in a fashion that is not area intensive.